The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit which can be used in general-purpose processors, signal processors, video processors and the like including logic circuits.
Among circuitries using pass-transistors, there have been introduced differential pass-transistor logics as described in IEEE Journal of Solid-state Circuits, Vol.SC-22, No.2, Apr.1987, pp.216-222 (will be called the first prior art) and complementary pass-transistor logics as described in IEEE Journal of Solid-state Circuits, Vol.SC-25, No.2, Apr.1990, pp.388-395 (will be called the second prior art). These circuitries are complementary logic circuits using both inverting and non-inverting logics.
Pass-transistor circuits using single-channel MOSFETs, instead of complementary MOSFETs, and a design scheme of pass-transistor circuits of the standard cell scheme are described in Custom Integrated Circuits Conference 1994 Digest, pp.603-606 (will be called the third prior art).
A configuration scheme of pass-transistor circuits based on a logic expression called a binary decision diagram is described in the Proceeding of 1994 Autumn Convention of The Institute of Electronics, Information and Communication Engineers of Japan, edition of fundamentals and interfaces, p.64 (will be called the fourth prior art).
A logical operation scheme based on the binary decision diagram is described in IEEE, Transaction on Computers, Vol.C-35, No.8.Aug.1986, pp.677-691 (will be called the fifth prior art).
Logic circuits for accomplishing logics of exclusive-OR circuits, full adders and the like based on a scheme of supplying an output signal of a preceding-stage complementary pass-transistor circuit to the gates of complementary MOSFETs of a succeeding-stage complementary transistor circuit are described in Japanese Laid-Open Patent Application No. 1-216622 (will be called the sixth prior art).
Logic circuits for accomplishing logics of exclusive-OR circuits, full adders and the like based on a scheme of supplying an output signal of a preceding-stage complementary pass-transistor circuit to the sources of complementary MOSFETs of a succeeding-stage complementary transistor circuit are described in Japanese Laid-Open Patent Application No. 1-256219 (will be called the seventh prior art).
A parity detection and generation circuit using exclusive-OR circuits based on a scheme of supplying an output signal of a preceding-stage complementary pass-transistor circuit to the gates of complementary MOSFETs of a succeeding-stage complementary transistor circuit and a scheme of supplying a output signal of another preceding-stage complementary pass-transistor circuit to the source of a complementary MOSFET of the succeeding-stage complementary transistor circuit are described in U.S. Pat. No. 4,477,904 (will be called the eighth prior art).